Uyemura, J. P. (2006). Chip design for submicron vlsi: Cmos layout and simulation. Cengage Learning.
Chicago Style (17th ed.) CitationUyemura, John P. Chip Design for Submicron Vlsi: Cmos Layout and Simulation. Cengage Learning, 2006.
MLA (8th ed.) CitationUyemura, John P. Chip Design for Submicron Vlsi: Cmos Layout and Simulation. Cengage Learning, 2006.
Warning: These citations may not always be 100% accurate.