Essential VHDL : RTL synthesis done right
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Saint Joseph's University
1999
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ukdwlib-105132016-08-08 00:00:00Perpustakaan UKDWEssential VHDL : RTL synthesis done right1. VHDL -- Hardware description language -- system analysisSaint Joseph's University1999TEXTISBN:0-9669590-0-0Asing |
| institution |
Universitas Kristen Duta Wacana Yogyakarta |
| collection |
Perpustakaan Yogyakarta |
| language |
Asing |
| topic |
1. VHDL -- Hardware description language -- system analysis |
| spellingShingle |
1. VHDL -- Hardware description language -- system analysis Essential VHDL : RTL synthesis done right |
| description |
|
| format |
TEXT |
| title |
Essential VHDL :
RTL synthesis done right |
| title_short |
Essential VHDL :
RTL synthesis done right |
| title_full |
Essential VHDL :
RTL synthesis done right |
| title_fullStr |
Essential VHDL :
RTL synthesis done right |
| title_full_unstemmed |
Essential VHDL :
RTL synthesis done right |
| title_sort |
essential vhdl :
rtl synthesis done right |
| publisher |
Saint Joseph's University |
| publishDate |
1999 |
| isbn |
ISBN:0-9669590-0-0 |
| _version_ |
1742307419260715008 |